Integrated semiconductor memories can be classified according to the storage time for stored information. Volatile semiconductor memories, such as DRAMs (Dynamic Random Access Memories), have memory cells, which store the written information only for fractions of seconds and therefore have to be continually refreshed. In nonvolatile semiconductor memories, on the other hand, stored information is retained over a long period, typically several years, even after the power supply is turned off.
A particularly space-saving arrangement of memory cells is attained in semiconductor memories whose memory cells have layer stacks, requiring no kind of selection transistor, at locations at which bit lines and word lines cross. In such memory types, called “cross-point arrays,” the substrate area, which is required per memory cell is obtained from the grid dimension of the bit lines and word lines.
This design can be used to fabricate semiconductor memories, for example, whose storage medium is a solid electrolyte. A layer stack, which contains both a layer comprising the solid electrolyte and the metallic layer, is connected to interconnects on opposite sides. The interconnects, which can be called bit lines and word lines, for example, can be used to apply electrical voltages. The layer stack, which is arranged between a bit line and a word line, respectively, has a current flowing through it when the voltage is applied between the bit line and the word line. The magnitude of this current is dependent on the nonreactive resistance of the layer stack.
On one side of a layer formed from a solid electrolyte, the layer stack has a metallic layer. Depending on the direction of current and the level of the applied voltage, metal ions coming from the metallic layer diffuse either into the layer from the solid electrolyte, or from the latter back into the metallic layer. When the metal ions, which have diffused into the layer comprising the solid electrolyte have diffused as far as the solid-electrolyte layer's boundary face, which is remote from the metallic layer, the nonreactive resistance of the layer stack is reduced overall; the nonvolatile memory cell is switched to low impedance, which corresponds to a programmed memory state, for example. By contrast, when a sufficiently high voltage of opposite polarity is applied, the metal ions diffuse out of the solid electrolyte again, i.e., back into the metallic layer. This restores a high-impedance state of the memory cell. This high-impedance state of the memory cell corresponds to an unprogrammed memory state, for example.
Nonvolatile semiconductor memories of the design described above are known by the name PMC (Programmable Metallization Cell) or else CBRAM (Conductive Bridging Random Access Memory). Memory cells of this type are elements, which switch resistively, i.e., on the basis of resistance. The magnitude of the nonreactive resistance of the layer stack in each individual cell represents an item of memory information which signifies a digital “0” or “1,” depending on whether the layer stack is at high impedance or low impedance, respectively. Physically, the stored item of information is obtained from the distribution of the metal ions within the solid electrolyte, which have diffused in. This distribution and the resultant memory state (high impedance or low impedance) can be read by applying a measurement voltage between the bit line and the word line to which the memory cell is connected.
Solid-electrolyte memory cells have no precise limit values (identical for all the memory cells in the same memory circuit) for those threshold voltages at which the transition from the high-impedance state to the low-impedance state or vice versa occurs. By way of example, the minimum value for the erasure voltages at which an originally low-impedance memory cell changes to high impedance varies within the same memory circuit from cell to cell. Similarly, the minimum value for the writing voltage (negative arithmetic sign) above which an originally high-impedance memory cell changes to low impedance varies from cell to cell. Instead of discrete threshold voltages, today's solid-electrolyte semiconductor memories thus have threshold voltage ranges of comparatively large bandwidth for the voltages, which are to be applied, which are required for reprogramming the memory cells. The bandwidths of the threshold voltages are also not inconsiderable in comparison with the mean value of the respective threshold voltage. Frequently, the bandwidth of the erasure voltages (i.e., the distribution of the memory-cell-specific values of the minimum erasure voltage) over the applied voltage is greater than the bandwidth of the writing voltages, i.e., the programming voltages. In particular, even the smallest possible erasure voltage at which at least some memory cells, if biased with this voltage, change to high impedance is lower than the absolute value of that writing voltage at which at least one of the memory cells, if biased with this writing voltage, changes to low impedance.
The absolute values of the threshold voltages for the two reprogramming operations, namely the erasure voltages and the writing voltages, are thus not the same. Even the random distributions of the level of the erasure voltages and the level of the writing voltages are not symmetrical with respect to one another for a reversal of arithmetic sign in the applied voltage. By way of example, if a negative voltage with a particular absolute value already reliably brings about programming, i.e., writing to a memory cell, specifically regardless of which individual memory cell is biased with it, then it is not yet inevitable that a (positive) erasure voltage with the same absolute value must bring about an erasure operation in the memory cell which is biased with it. The reason is that the wider distribution of the erasure voltages in comparison with the writing voltages means that the memory circuit contains memory cells, which do not change to high impedance until the erasure voltages are even higher.
Since the memory state in a semiconductor memory, i.e., the level of the nonreactive resistance of the respective memory cell, needs to be clearly defined, the voltages applied for the purpose of a writing or erasure operation need to be outside of the bandwidths of the writing voltages and the erasure voltages.
A voltage for a reprogramming operation is applied between the bit line and the word line. However, since a solid-electrolyte semiconductor memory, in the form of a cross-point array, has a multiplicity of memory cells connected to each bit line and each word line, but there are no selection transistors present, applying the respective programming voltage exclusively via the bit line or exclusively via the word line would respectively reprogram all the memory cells which are connected to the respective line. For this reason, to write an item of information to a memory cell, the necessary writing voltage is applied to the bit line and to the word line in the form of two voltage components, which together provide the necessary writing voltage. By way of example, the potential of the bit line to which the memory cell is connected is increased by a particular absolute value and at the same time the potential of the word line to which the memory cell is connected is lowered by a particular absolute value.
However, since a cross-point array has no selection transistors in it, the voltage components are simultaneously also applied to those layer stacks which are connected to the same bit line but a different word line, or to the same word line but a different bit line. If they are situated within the bandwidth of the erasure voltages or the bandwidth of the writing voltages, or their absolute value is even greater, these voltage components can result in inadvertent reprogramming of further memory cells.
At least for a programming operation, i.e., a writing operation, these voltage components can be chosen to be below these lower bandwidth limits, so that exclusively the memory cell situated at the cross point between the selected bit line and the selected word line is programmed. This is possible because the bandwidth of the writing voltages in the case of solid-electrolyte memory circuits is so small that a voltage, which is half the magnitude of a writing voltage, sufficiently high for reliable programming, has an absolute value which is so small that it is situated outside of the bandwidth of the threshold voltages for the programming operation.
For the converse reprogramming operation, namely erasure, the even larger bandwidth of the erasure voltages in solid-electrolyte semiconductor memories means that selective access to individual memory cells is not known. Instead, whole rows, columns or blocks of memory cells, which are actuated by the same respective group of bit lines and word lines or of first and second lines, would need to be erased simultaneously. There is thus not yet any known way of erasing individual memory cells selectively in solid-electrolyte semiconductor memories.
It would be desirable to provide an integrated semiconductor memory having resistively switching memory cells whose memory cells can be erased independently of one another and selectively in relation to the respective other memory cells. In particular, the semiconductor memory to be provided needs to allow selective access to individual memory cells during erasure even in the case of solid-electrolyte memory cells whose erasure voltages are distributed over a wider voltage range than their writing voltages. Another aim is to provide a method, which can be used to perform a selective erasure operation on individual memory cells of such a semiconductor memory.